The present invention relates in general to semiconductor technologies and, in particular, to complementary metal oxide semiconductor integrated circuit (CMOS IC) devices and manufacturing methods thereof. More particularly, but not exclusively, this invention relates to a method of controllably forming a well impurity profile at or near well boundaries or interfaces in semiconductive substrates.
An explanation will first be given of problems faced with prior known well-region formation technologies in conjunction with one typical case of a CMOS integrated circuit (IC) device. The explanation begins with a brief description of some major process steps in the manufacture of such CMOS IC including element isolation and well formation procedures with reference to FIGS. 1 to 5.
Referring to FIG. 1, a substrate 101 has its surface on which a buffer oxide film 102 is formed to a thickness of, for example, 35 nanometers (nm). In this case the substrate 101 may be of either N type or P type. Then, a first stopper layer 103 is deposited by chemical mechanical polishing (CMP) techniques on the buffer oxide film 102. The stopper 103 is made of a chosen material less in polishing rate than oxide films, such as SiN or polycrystalline silicon (polysilicon). Next, a mask layer (not shown) is deposited such as tetraethylorthosilicate (TEOS) oxide film or the like.
The resultant structure is coated with a resist layer (not shown) on the mask layer, which resist is then subject to patterning in a way such that the resist is partly removed away in selected regions in which grooves, called xe2x80x9ctrenchesxe2x80x9d 104, are to be formed. Subsequently, the mask material is selectively removed. Thereafter, the resist is peeled off for sequential etching of the first stopper 103 and buffer oxide film 102 in this order; further, trenches 104 are formed in the substrate 101 as shown in FIG. 1.
Then, as shown in FIG. 2, the inner walls of each trench 104 are oxidized, causing an oxide film 105 of TEOS or the like to be deposited within the trench 104, thereby providing a buried oxide film. And, a chosen material that is low in polishing rate is deposited, which is then selectively removed at locations other than certain regions in which the trenches 104 of large area exist, to thereby form a second stopper layer. Note that the second stopper material is not depicted herein in view of the fact that such will not be required when the large-area trenches are absent. Thereafter, the resulting device structure is subject to surface planarization using CMP techniques.
Then, as shown in FIG. 3, the first stopper layer 103 is peeled off.
Then, as shown in FIG. 4, a well region of N type conductivity (N-well) 106 is formed in a substrate region in which a P-type transistor is to be formed, whist a P-type well (P-well) 107 is defined in a region selected for formation of an N-type transistor therein. Ion implantation is then performed with respect to those regions that will become channels in such a way as to permit each transistor to have a desired electrical characteristics. When this is done, the impurity profile is controlled in a way as will be described later.
After the buffer oxide film 102 is removed away from the overall surface of the substrate 101, a gate oxide film 108 is formed on the surface of substrate 101; then, a gate electrode 109 is formed thereon. Subsequently, ion implantation is done, forming a lightly doped drain (LDD) (not shown) in the surface of the substrate 101. After sidewalls 110 are formed, ion implantation and thermal processing are carried out, forming diffusion layers 111 and 112.
Then, as shown in FIG. 5, a dielectric film 113 made of SiO2 or the like is deposited as a first interlayer film. This dielectric film 113 is selectively removed in those regions for use in forming contact holes for electrical interconnection. Here, a first lead wire pattern 114 is formed, which may be a chosen conductive material.
Thereafter, second and third interlayer dielectric films may be formed along with chip lead patterns where necessary, although these are not depicted herein. After formation of these lead patterns, a protective film 115 made of SiN or the like is formed overlying the resultant surface, to thereby complete a CMOS IC device.
An explanation will next be given of the element isolation breakdown voltage at well boundaries as well as a scheme for maintaining the breakdown voltage.
FIGS. 6 to 8 are diagrams each illustrating, in cross-section, the well structure near the boundary of a well region of the CMOS IC as manufactured through the process steps shown in FIGS. 1-5. Parts or components identical to those of FIG. 5 are designated by identical reference numerals, and an explanation thereof will be omitted herein.
Suppose that in the state shown in FIG. 6, a bias voltage VN of the positive polarity is applied to a heavily doped N type (N+ type) diffusion layer 112 in a P-well 107 while the N-well 106 and P-well 107 are biased at zero volts. In this case, the junction between N+-diffusion layer 112 and P-well 107 is in the xe2x80x9creversexe2x80x9d direction, wherein no currents attempt to flow therein. However, as the bias voltage VN increases in potential value, a depletion layer 117 between the N+-diffusion layer 112 and P-well 107 behaves to expand toward the P-well 107, as designated by arrow xe2x80x9cAxe2x80x9d in FIG. 6.
Then, as shown in FIG. 7, the P-well 107 laid between the N+-diffusion layer 112 and N-well 106 is fully depleted. When this is done, punch-through can take place between the N+ diffusion 112 and N-well 106, causing a current to flow in the direction denoted by arrow C1. The potential value of bias voltage VN at this time is called the xe2x80x9cisolation breakdownxe2x80x9d voltage among those skilled in the semiconductor art.
Obviously, the isolation breakdown voltage must be significant relative to the power supply voltage used. To potentially increase the breakdown voltage, it should be required that the trench increase in depth lengthening the isolation/separation distance (denoted by arrow B1 in FIG. 6); or alternatively, the P-well 107 is required to increase in impurity concentration thereby limiting the expansion of the depletion layer 117. Note here that an approach for increasing the trench width in order to lengthen the separation distance is not preferable in view of the integration density; accordingly, this approach is not practiced excessively. For example, assume that the trench depth is 0.7 micrometers (xcexcm), the separation width is 0.4 xcexcm, and the power supply voltage used is 3.3 volts. If this is the case, impurity concentration might be designed permitting a peak concentration of 1.0 to 5.0xc3x971017 atoms per cubic centimeter (cm-3) to appear at or near the bottom of each trenchxe2x80x94namely at the depth of 0.8 to 0.9 xcexcm).
Next, consider that the N-well 106 is biased at VNW (positive bias voltage) whereas the N+-diffusion layer 112 within P-well 107 and the P-well 107 are kept at zero volts, as shown in FIG. 8. In this case, a multilayer structure consisting of the N-well 106 and buried oxide film 105 plus P-well 107 is equivalent to the gate/gate-oxide/P-well structure in N type MOS (NMOS) devices, wherein upon biassing of the N-well 106, certain part of the P-well 107 along the trench side surface acts to invert as shown by wavy line D in FIG. 8, forming a channel. Thus, a current attempts to flow in the direction designated by arrow C2. This results in operation of a vertical-structured parasitic MOS transistor. When this is done, the effective separation distance designated by arrow B2 in FIG. 8 decreases, lowering the isolation breakdown voltage accordingly.
More specifically, when comparing the case of biasing the N+ diffusion layer 112 within the P-well 107 to the case the N-well 106 is biased, the latter tends to exhibit a decrease in breakdown voltage. One way of improving the breakdown voltage in the latter mode is to increase the threshold value of such inherent parasitic MOS transistor element by increasing the impurity concentration of P-well 107 to thereby decrease the risk of inversion. This can be said because even when the trench is rendered deeper, the effective separation distance is kept unchanged if the parasitic MOS transistor becomes operative.
FIGS. 9-10 are graphs demonstrating a profile of impurity concentration distribution in the P-well as modified to suppress the operability of the vertical parasitic MOS transistor stated supra, wherein FIG. 9 shows the profile before modification whereas FIG. 10 shows the profile after modification.
As apparent from viewing FIG. 9, the xe2x80x9cnativexe2x80x9d profile before modification is low in well concentration in the substrate surface, which would result in the so called xe2x80x9cretrograde-wellxe2x80x9d region capable of achieving reduced threshold value and low junction capacitance. To suppress or eliminate the operation of a parasitic MOS transistor element, it may be effective to add ion implantation process, permitting the resultant profile to have an impurity peak at or near a location with its depth half of the trench depth. One example is that where a well profile has its impurity peak of approximately 1.0 to 5.0xc3x971017 cmxe2x88x923 at the depth of 0.8 to 0.9 xcexcm, additional ion implantation is performed correcting the well profile so that it has a peak at the depth approximately half the trench depth, i.e. 0.3 to 0.4 xcexcm deep.
Unfortunately, this does not come without accompanying a penalty: in the case the well profile is so modified, the resulting impurity concentration at the substrate surface does increase relative to the xe2x80x9coriginalxe2x80x9d retrograde well region as shown in FIG. 10. This makes it impossible to reduce the threshold value, which in turn results in an undesired increase in diffusion junction capacitance, which can lead to a serious bar to the operability of a CMOS IC device.
An explanation will then be given of a technique for separately forming well regions using separate masks in order to avoid the aforesaid problems.
FIG. 11 depicts, in cross-section, a semiconductor device at a stage immediately after completion of the well region formation process. At this time, as shown in a well profile of FIG. 13, the individual well region remains uniform in impurity concentration as a whole, and thus is considered as a retrograde well.
Then, as shown in FIG. 12, the structure is subject to patterning process by use of a resist 119 to ensure that ions are doped or implanted into only selected portions of the N-well region 106 and P-well region 107 near or around the well boundary or xe2x80x9cinterfacexe2x80x9d at a later lithography process step. Subsequently, ions are additionally doped by ion implantation techniques causing the resultant structure to exhibit the well profile shown in FIG. 10. In this case, the resulting well profile of the remaining part of N-well region 106 other than the well boundary region is as shown in FIG. 14. A well profile of an N-well region 116 at the well boundary is as shown in FIG. 15.
With the foregoing approach, the intended low threshold value and low junction capacitance may be achievable because the well profile of those regions other than the well boundary region remains unchanged. However, this prior art approach is encountered with a problemxe2x80x94two extra masks and two separate lithography process steps should be required as those skilled in the art would readily appreciate that the prescribed process must be applied to the individual one of the N-well and the P-well in a way independent of each other. In addition, by taking account of execution of such extra lithography procedures with extra masks used, this approach is difficult in successful reduction to practice due to the risk of unacceptable position alignment deviations during such repetitive processing.
It has been described that while it is required that the impurity concentration of well regions be set higher in order to eliminate a decrease in isolation breakdown voltage due to unwanted operation of an inherently existing vertical parasitic MOS transistor element near the well boundary, such increase in well impurity concentration would result in difficulty of low threshold value attainability while undesirably increasing the junction capacitance concerned. In addition, while the breakdown voltage is improvable by adding ion implantation process for the well boundary region only, this approach suffers from the need for additional masks and extra process steps, thus increasing complexity of the CMOS-IC fabrication.
It is therefore an object of the present invention to provide an improved semiconductor device and its manufacturing method capable of readily improving the isolation breakdown voltage while achieving low threshold value and low junction capacitance, by attaining by an easy method a well structure with xe2x80x9cvariablexe2x80x9d well concentration which is high at or near well boundary regions and yet low in element formation regions.
To attain the foregoing object, the present invention provides a method for manufacturing a MOS semiconductor device, which method is featured by including a first step of forming a groove in an element isolation region of a semiconductor substrate, a second step of burying an element isolation dielectric film within the groove, a third step of selectively depositing an ion deceleration material on part or parts of the element isolation dielectric film between an element formation region of a first conductivity type and an element formation region of a second conductivity type, which material is to slow or decelerate those ions being doped or implanted into the element formation regions of the first and second conductivity types at locations near the interface between these regions and the element isolation dielectric film, a fourth step of performing first ion implantation for a respective one of the element formation regions of the first and second conductivity types to thereby form a well region in therein, and a fifth step of doing second ion implantation for each of the element formation regions with a profile different from that of the first ion implantation.
In accordance with another aspect of this invention, a CMOS semiconductor device manufacturing method is featured by including a first step of selectively forming a deposition film in an element formation region of a first conductivity type and an element formation region of a second conductivity type in a semiconductor substrate, a second step of forming a groove in an element isolation region of the semiconductor substrate in the state that the deposition film was formed in the element formation regions of the first conductivity type and second conductivity type of the semiconductor substrate, a third step of depositing an element isolation dielectric film on the semiconductor substrate including the groove interior, a fourth step of causing the element isolation dielectric film to regress or xe2x80x9cretrogradexe2x80x9d with the deposition film being as a stopper to the extent that an entire surface of the semiconductor substrate is planarized, a fifth step of permitting the element isolation dielectric film to project for deceleration of ions being implanted at nearby locations of an interface between each of the element formation regions of the first and second conductivity types and the element isolation dielectric film during ion implantation to the element formation regions of the first and second conductivity types with the resultant exposed deposition film removed away, a sixth step of performing first ion implantation to form a well region in a respective one of the element formation regions of the first and second conductivity types, and a seventh step of performing second ion implantation for the element formation regions with a profile different from that of the first ion implantation.
In accordance with a further aspect of the invention, a semiconductor device includes a semiconductor substrate, an element formation region of a first type conductivity and an element formation region of a second type conductivity in the semiconductor substrate, a groove as formed between the element formation region of the first type conductivity and the element formation region of the second type conductivity, an element isolation dielectric film deposited in the groove, and a first region in close proximity to the element isolation dielectric film in the element formation region of the first type conductivity, and a second region different from the first region in the element formation region of the first type conductivity, wherein the first region has an impurity concentration profile with a first concentration peak laid midway between the substrate surface and the bottom of the groove and further with a second concentration peak near the groove bottom.
One significant feature of the invention lies in that the ion implantation is performed after disposal of either an ion deceleration film of a chosen material with a preselected thickness or a projection portion of the element isolation dielectric film only at selected part of the element formation regions, which part may overlie the well boundary region. This may result in that the concentration peak of the well profile at a well boundary or interface is positionally shifted or xe2x80x9coffsetxe2x80x9d toward a shallower location from the semiconductor substrate surface. With such an arrangement, while the impurity concentration peak inherently appears at or near the bottom of the buried element isolation region, appropriate adjustment of the ion implantation condition forces the peak of impurity concentration profile to be offset toward the shallower location solely in the well boundary region in which a retrograde well is present, thus making it possible to eliminatexe2x80x94or at least greatly suppressxe2x80x94inversion of a parasitic MOS transistor component, which in turn enables decrease of masks and process steps required.
Other objects, features, and advantages of the present invention will become apparent form the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.